The present invention relates to semiconductor memory devices. More particularly, the present invention is directed to a multi-plane semiconductor memory device and a block management method of the same.
Semiconductor memory devices are storage units capable of storing and releasing data, as needed. Semiconductor memory devices are generally classified as random access memories (RAMs) and read-only memories (ROMs). RAMs, called volatile memories, lose stored data when there is no power supply. ROMs, called nonvolatile memories, retain stored data even without power supply. Flash memories are currently widely used as a type of nonvolatile storage unit.
In a traditional flash memory, all memory blocks are located on a single plane. This is called single-plane structure. Erasing operations are performed in block units. In a flash memory having a single-plane structure, a command is available to a block unit in an erasing mode, and to a page unit in programming and reading modes.
For the purpose of enhancing performance of semiconductor memory devices, a multi-plane structure has been proposed. In a multi-plane semiconductor memory device, blocks are distributed over multiple planes. An advantage of such a multi-plane structure is that erasing, programming and reading operations can be simultaneously executed on blocks or pages, even when placed independently on different planes. Blocks operating at the same time are arranged successively over adjacent planes. Such an assembly of simultaneously operating blocks is referred to as a “multi-plane operation group.”
FIGS. 1A and 1B are block diagrams respectively showing single and multiple plane structures. FIG. 1A illustrates the single plane structure, while the FIG. 1B illustrates the multiple plane (or multi-plane) structure.
As shown in FIG. 1A, the flash memory includes a single plane PLN0, having multiple blocks BLK0˜BLKn−1. This architecture is referred to as “single plane structure.” In the single plane structure, a flash operation is executed on a block by block basis. The flash operation may include programming, reading and erasing actions. In response to an external request for flash operations on the blocks BLK0 and BLK1, for example, a second flash operation OP2 is conducted for the second block BLK1 only after a first single flash operation OP1 is completed for the first block BLK0. In other words, a single flash operation is executed twice, respectively, for the two blocks BLK0 and BLK1.
The flash memory shown in FIG. 1B includes two planes PLN0 and PLN1. Each plane includes multiple blocks BLK0˜BLKn−1. This architecture is referred to as “multi-plane structure.” In the exemplary multi-plane structure illustrated in FIG. 1B, there are two planes, although it is understood that a multi-plane structure may include more than two planes.
In the multi-plane semiconductor memory, the blocks are dispersed on more than one plane. Further, simultaneous flash operations may be conducted for the blocks successively arranged over adjacent planes. In other words, a flash operation can be executed for multiple blocks at the same time in the multi-plane structure. Referring to FIG. 1B, responding to an external operation request for the blocks BLK0 and BLK1, for example, a multi-flash (or multi-plane) operation OP1 is executed once for both blocks BLK0 and BLK1. As a result, the two blocks BLK0 and BLK1 are treated at one time in the multi-plane operation OP1.
The multi-plane operation is referred to as an expansion of the single plane operation. For example, if the memory includes four planes, the programming operation can be carried out simultaneously for four adjacent pages over the four planes. In particular, data are first loaded into page buffers corresponding to the four pages on the four planes. After filling the four page buffers with data, the four pages on the four planes are respectively programmed at the same time. Thus, it is possible to shorten programming time, as compared to individually programming the pages.
As previously discussed, while the single plane semiconductor memory is operable with an on-block flash operation, the multi-plane semiconductor memory enables improved performance because it performs simultaneous flash operations for multiple blocks successively arranged over multiple planes adjacent to each other. Therefore, the multi-plane structure effectively enhances the performance of semiconductor memory devices.
However, when a bad block appears in a flash memory, it is necessary to detect and replace the bad block with a valid block in order to assure reliable performance of the flash memory. A bad block is one in/from which data cannot be stored/read successfully. Bad blocks may be included a flash memory, or generated later due to a variety of causes. A multi-plane semiconductor memory may be especially affected by replacement problems with respect to bad blocks.